The present invention relates to semiconductor structures, and particularly to electrical antifuses that are compatible with another semiconductor structure having a replacement gate electrode and methods of manufacturing the same.
Electrical fuses and electrical antifuses are used in the semiconductor industry to implement array redundancy, field programmable arrays, analog component trimming circuits, and chip identification circuits. Once programmed, the programmed state of an electrical fuse or an electrical antifuse does not revert to the original state on its own, that is, the programmed state of the fuse is not reversible. For this reason, electrical fuses and electrical antifuses are called One-Time-Programmable (OTP) memory elements.
Programming or lack of programming constitutes one bit of stored information in fuses or antifuses. The difference between fuses and antifuses is the way the resistance of the memory element is changed during the programming process. Semiconductor fuses have a low initial resistance state that may be changed to a higher resistance state through programming, i.e., through electrical bias conditions applied to the fuse. In contrast, semiconductor antifuses have a high initial resistance state that may be changed to a low resistance state through programming.
Continuous advances in the semiconductor technology oftentimes require changes in the material employed in semiconductor structures. Of particular relevance is the advent of a replacement gate electrode technology for field effect transistors, which employs formation of a dummy gate electrode prior to formation of source and drain regions. After formation of a gate-level dielectric layer and subsequent planarization, the material of the dummy gate is removed. Some versions of the replacement gate technology enable formation of a gate dielectric after removal of the dummy gate to avoid high temperature treatment and consequent thermal decomposition of the gate dielectric. Other versions of the replacement gate technology formed gate conductors without replacing a gate dielectric, which is formed before formation of the dummy gate. In this case, multiple types of gate materials may be employed for different devices for optimized performance.
A challenge that the replacement gate technology poses is formation of other devices without adding excessive processing cost by sharing the same manufacturing processing steps with field effect transistors as much as possible. OTP memory elements are among such devices that are constrained in terms of processing sequences. Cost-effective and reliable OTP memory elements that are compatible with replacement gate technology are thus desired.